Initially, it might seem that the CISC philosophy is dead. On the contrary, CISC is more relevant than ever because there is a slowdown, if not the end, of Moore’s law. As of 2020, there are only three major companies Intel, TSMC, and Samsung left at the bleeding-edge of semiconductor manufacturing. Previous titans such as Global Foundries are reducing their investment in newer nodes and processes. With that in mind, we can’t rely on steady improvements to general purpose computing. Instead, hardware will grow more complex to support specialized developer needs. However, what happens when specialized hardware functionality is added year-on-year to meet the current fads? It’s not exactly trivial to deprecate hardware functionality. Will we have huge and bloated instruction sets? It’s not hard to imagine an ISA that has upwards of 5k instructions. Thus, I feel we need to reinvestigate the CISC philosophy to make hardware complexity manageable.

Examples of Current Complexity

• Why do ARM chips have an instruction with Javascript in the name?
• Intel’s RDRAND
• Intel’s AVX
• Transactional memory support in IBM Power 8 Processor
• Neural Engine in Apple’s A11

Complex Hardware Blurbs and Questions

• Hardware transactional memory could simplify concurrency. It could make previously tricky STM a reality. STM can be backed by hardware primitives for increased performance.
• NUMA-awareness (not to be confused with the Numa Numa song) will be needed. More complex processor topologies are being invented. My understanding is that many operating systems e.g. Windows don’t take into account differences between AMD’s CCX and traditional Intel multiprocessor systems glued together by QPI. Additionally, exotic storage solutions e.g. 3D XPoint can be used as Non-volatile main memory which also change assumptions about memory.
• Will neuromorphic chips e.g. IBM’s TrueNorth and Apple Neural Engine become popular?
• What APIs will be offered to access specialized hardware? My understanding is that Apple’s neural engine can’t be accessed using traditional assembler instructions. You must use CoreML.
• Will mainstream CPUs include a FPGA or FPGA-like coprocessor?